1. Technical Field
The present invention relates to an active matrix liquid crystal display device, more particularly to a thin film transistor (hereinafter referred to as TFT) array which serves as a switching device for operating the liquid crystal display device and a method of fabricating the same.
2. Prior Art
Liquid crystal display devices (hereinafter referred to as LCD) have been wisely used. While the LCD has been desired to display a high quality picture image, a demand for a low cost of the LCD has been more increased. Accordingly, a structure of the LCD capable of being fabricated in the small number of fabrication steps and achieving a high throughput has been strongly desired. A method of fabricating such LCD has also been desired for similar reasons.
The TFT functions as a switching device that is one of important components to operate the LCD. The fabrication of the TFT array structure requires the considerable number of fabrication steps in the total LCD fabrication steps, and hence requires a high fabrication cost. Moreover, since a defective ratio in each of the steps is multiplied with others, a reduction in a yield rate is brought about due to a large number of fabrication steps. Accordingly, a reduction in the number of steps for fabricating the TFT array structure is convinced to contribute significantly to reduce a cost of the LCD incorporating the TFT. For this reason, in stead of a reverse stagger structure and a bottom gate TFT structure shown in FIG. 1(b) which have been heretofore adopted generally, a stagger structure which can be fabricated in fewer photolithography steps, that is, a top gate TFT structure shown in FIG. 1(a), has been attracted.
The top gate TFT structure can be theoretically fabricating with two photo-masks. However, since a channel region is normally made of a semiconductor exhibiting a photoconductive property, amorphous silicon (a-Si), photo-induced leak current is caused due to exposure to external light or a backlight through a transparent substrate such as glass, thus causing problems of such significant deterioration in a display quality of the LCD and an erroneous operation thereof. Therefore, a light shielding layer must be provided at a lower portion of the top gate TFT structure. The light shielding layer is normally made of metallic material. To allow light to transmit through a pixel portion and to prevent an occurrence of parasitic capacitance in a wiring portion owing to a metal/dielectric/semiconductor structure, the light shielding layer made of the metallic material must be removed in the pixel portion and the wiring portion. Accordingly, another mask is further required to pattern the light shielding layer. In the end, to fabricate the top gate TFT structure, at least three masks are needed.
In Japanese Patent Laid-Open No. Hei 9(1997)-68727, a technology in which a light shielding layer and an a-Si layer are formed by the same pattern is disclosed. In this gazette, three masking processes using a mask for forming a gate electrode and a gate insulating layer, a mask for patterning the a-Si layer and the light shielding layer and a mask for forming pixel electrodes and signal lines are disclosed. In the TFT structure in which the a-Si layer and the light shielding layer are formed by the same pattern, a light which is made to be incident perpendicularly onto the light shielding layer is shielded by the light shielding layer. However, a light such as a scattered light, which is made to be incident onto the light shielding layer from directions other than the vertical direction, cannot be shielded sufficiently by the light shielding layer. Thus, the incidence light reaches the edge portion of the a-Si layer, and photo-induced leak current may occur.
The object of the present invention is to provide a method of fabricating a TFT structure using a fewer number of masks, accordingly, in a fewer number of fabrication steps.
Another object of the present invention is to provide a TFT structure free from a problem of photo-induced leak current and exhibiting a high reliability, and a method of fabricating the same.
According to the present invention, a method of fabricating a TFT structure by two masking processes is provided. The method of fabricating a TFT structure of the present invention comprises the steps of: depositing a light shielding layer on a substrate; depositing an interlayer insulating layer on the light shielding layer; forming source/drain electrodes on the interlayer insulating layer (a first masking step); and depositing a semiconductor layer, a gate insulating layer and a gate metal layer on the interlayer insulating layer sequentially so as to cover the source/drain electrodes; etching the gate metal layer, the gate insulating layer and the semiconductor layer using a resist pattern for use in forming a gate electrode (a second masking step); and etching the interlayer insulating layer and the light shielding layer using the source/drain electrodes as a mask.
The TFT structure fabricated by the method of the present invention has a structure that the semiconductor layer and the light shielding layer are formed in alignment with each other, and a periphery of the semiconductor layer is inside of a periphery of the light shielding layer and does not cross the periphery of the light shielding layer. Accordingly, in case that a scattered light exists, no photo-induced leak current at an edge region of the semiconductor layer occurs.
Moreover, by properly selecting the combination of insulating substances forming the interlayer insulating layer and the gate insulating layer, it is possible to utilize etching selectivity of these insulating substances. Thus, the structure that the periphery of the semiconductor layer is inside of the periphery of the light shielding layer can be obtained without requiring any additional step. To be more specific, the interlayer insulating layer is made of an insulating substance containing SiOX and SiOXNY as a main component, and the gate insulating layer is made of an insulating substance containing SiNX as a main component. When a plasma etching is performed using a mixed gas containing CF4 and hydrogen, the gate insulating layer and the semiconductor layer are naturally over-etched compared to the interlayer insulating layer.